Battery systemsMobility

EV battery pack

An electric-vehicle battery pack as one multi-domain model — equivalent-circuit cells, a coupled thermal network, a CC-CV charge controller and an active balancer, composed cell → module → pack and run end to end.

DjiniousLabModelling & simulation

A 4-cell balancing module on the DjiniousLab canvas — four equivalent-circuit cells starting at different states of charge, wired through an active charge-shuttling balancer into per-cell state-of-charge scopes

≈345 V · 3.5 kWh pack: 96S2P≈345 V · 3.5 kWh pack
coupled domains: 3coupled domains
design notebooks: 11design notebooks
.djl compositions: 3.djl compositions
EKF SoC error: 0.07%EKF SoC error
fast charge to 80%: 3.1Cfast charge to 80%

An EV battery pack, modelled where the disciplines meet.

Cell electrochemistry, pack thermals, and the battery-management system don't live in separate tools here. A 96S2P NMC pack is built as one composition — equivalent-circuit cells coupled to a thermal network, wrapped in a closed-loop CC-CV charger and an active balancer — and solved together, electrical and thermal and control in a single elaboration.

One pack, composed from one cell.

A single equivalent-circuit cell is the atom; the module and pack are compositions of it. Each layer is its own runnable model, and they share one cell definition.

Equivalent-circuit cell

A Thevenin 1-RC cell — series resistance, one RC polarization pair, a non-linear OCV(z) curve and coulomb-counted state of charge — written once and reused at every level.

Thermal node

Ohmic and polarization loss become heat that drives a lumped thermal mass with convective bleed to ambient. Temperature is a first-class state, not an afterthought.

BMS charge control

A saturated-proportional control law reads pack voltage and commands a charge current — reproducing the textbook constant-current → constant-voltage envelope without any mode-switching events.

Active balancer

A charge-shuttling balancer moves charge between imbalanced cells toward the module mean — conserving total charge while the spread collapses in minutes.

State estimation

An Extended Kalman Filter fuses noisy voltage and biased current to track SoC online, where a bare coulomb counter would drift.

Safety envelope

An over-temperature throttle with hysteresis derates the charge current to hold the hottest cell at its cap — the BMS protecting the pack, in the loop.

A 4-cell active-balancing module on the DjiniousLab canvas: four BalCell blocks at SoC 1.00 / 0.92 / 0.85 / 0.80 wired through a Balancer4 block into four per-cell SoC scopes — The balancing module as a composition on the canvas — four cells starting 20% apart, an active charge-shuttling balancer, and a scope per cell. Run it and the spread collapses from 20% to under 0.5% in twenty minutes while the average SoC stays put; the dissipative-bleed alternative would take about ten hours.

Electrical, thermal and control, solved together.

The acausal electrical network, the per-cell heat path, and the signal-domain control loop are elaborated into one differential-algebraic system that a stiff Rodas5P solver integrates as a whole — no co-simulation hand-off, no manual time-stepping between tools. A 1C discharge of the cell drops SoC from full to 16.7%, sags the terminal from 4.10 V to 3.21 V, and lifts the cell about 1.4 °C, all from the same coupled equations. The same model exports as an FMI 2.0 co-simulation unit for Simulink, dSPACE and other FMI hosts.

A DjiniousLab notebook plotting |dOCV/dz| against state of charge for an NMC and an LFP cell — the NMC curve peaks sharply, the LFP curve stays low and flat — Why chemistry decides observability. The slope of open-circuit voltage against state of charge sets how much a SoC error shows up in a voltage reading — LFP's famously flat plateau is the classic estimation headache, and the model makes it visible before you commit to a chemistry.

An EKF that holds where a counter drifts.

Run the pack over a mixed charge/discharge profile with a noisy voltmeter and a biased ammeter. A pure coulomb counter — the cheap baseline — walks off to about 5% SoC error. The Extended Kalman Filter on the cell's [SoC, polarization] state corrects from the voltage residual and ends within 0.07% of truth, holding under ~0.7% after the first few minutes — comfortably inside a 2% accuracy budget.

DjiniousLab

True SoC (solid) versus the drifting coulomb counter (dashed) versus the EKF estimate — same wrong initial guess and same current bias, but the filter converges and tracks while the open-loop counter accumulates error.

The CC-CV envelope, from a single control law.

The charge controller commands a current proportional to the gap between pack voltage and the CV set-point, clamped to a maximum. Far from the set-point it saturates — that's the constant-current phase; as the pack fills, the command falls out of saturation and tapers — that's constant-voltage. Sweeping the current limit against peak temperature finds the knee: about 3.1C reaches 80% state of charge in 25 minutes while staying inside the thermal limit.

DjiniousLab

The recommended fast charge: pack voltage climbs while the current holds at its limit, then tapers as the constant-voltage phase takes over — 80% state of charge in 25.1 minutes, verified against the ≤45-minute requirement.

The details that decide correctness.

Charge-positive sign

Terminal current is defined positive into the + pin, so positive current charges. A discharge load forces +I into its own pin and Kirchhoff's law makes the cell see −I — get that backwards and the pack silently charges instead of discharging.

Causal heat path

The canvas engine rejects a single component that bridges two acausal domains, so the cell can't carry both an electrical and an acausal thermal port. Heat is emitted as a signal and integrated by a thermal block instead — same physics, a model that actually compiles.

The BMS algebraic loop

The charge current appears in the measured pack voltage through the ohmic drop, closing an algebraic loop. The saturated proportional law keeps it well-posed, and the solver resolves it every step — confirmed against an analytic CC→CV cross-check.

Charge-conserving balancing

Each cell exchanges a current proportional to its distance from the module mean. The corrections sum to zero, so the average SoC is preserved exactly while the spread decays — active shuttling, not dissipative burn-off.

Every claim is a number you can re-run.

The notebooks and .djl studies are gated on verified live-worker results, with the physics cross-checked by independent integration of the same equations.

Result

EKF SoC error: 0.07%
Active-balancing spread (20 min): 0.3%
Fast charge to 80% SoC: 25.1 min
Cycle life to 80% @ 25 °C: 781 cycles
Drive-cycle regen recovered: 28%

Target

EKF SoC error: ≤ 2%
Active-balancing spread (20 min): from 20%
Fast charge to 80% SoC: ≤ 45 min
Cycle life to 80% @ 25 °C: ≥ 500
Drive-cycle regen recovered: —

From text model to design twin.

The cell, module and pack are pure-text DJL. The parser lowers them to a flat intermediate representation, then to a ModelingToolkit symbolic system the Julia worker integrates — streaming live scopes back into the browser — and the catalog circuits export as functional FMI units. Eleven notebooks carry the engineering narrative end to end: OCV characterization, equivalent-circuit identification, thermal C-rate response, SoC estimation, balancing, BMS control, fast-charge trade-offs, cycle and calendar aging, and a full drive cycle — a design-iteration twin you exercise long before a cell is ever assembled.

Design-grade, equivalent-circuit fidelity.

The cell is an equivalent-circuit surrogate, not an electrochemical (Newman P2D / single-particle) model — it captures voltage, state of charge and lumped heat, not concentration gradients, plating or detailed degradation chemistry. OCV is a smooth analytic curve in the .djl atom and the realistic NMC/LFP shapes live in the notebooks; aging is empirical (Arrhenius throughput and calendar laws). What it is good for is exactly what pack and BMS design needs first: sizing series/parallel counts, choosing the thermal budget, tuning the charge and balancing strategy, and trading fast-charge speed against heat — on your own cell numbers, in minutes, before any hardware exists.