Djinious
RF & radar sensingAerospace & marine

Embedded Radar Sensing Module

An embedded radar sensing module — the system class the RF/radar recipe covers: a mixed-signal board where spectrum, EMC, environmental and fabrication standards constrain the design as hard as the sensing requirement does.

DjiniousEngineering
The ELANG source of the Kestrel-SAR III airborne L-band SAR imaging payload in the DjiniousEngineering editor: the project, its actors (an RF/SAR systems specialist, a payload integrator, an edge-compute supplier) and its performance requirements, each with an acceptance criterion and a verification method.
system code
RDRsystem codeELANG reference model
standards in the recipe
5standards in the recipeITU · IEC 61000 · IEC 60068 · IPC-2228 · IPC-6018

The regulations are part of the requirement set

For an RF system, spectrum allocation, EMC immunity, environmental endurance and board-fabrication rules are not compliance you bolt on at the end — they are constraints the architecture has to satisfy from the first trade.

The RF/radar recipe pulls them in as tracked obligations so the design is proven against them, not merely tested against them later.

Recipe and standards

Driven by the embedded RF/radar recipe, extending the electronics recipe.

ITU Radio Regulations

Spectrum limits, captured as constraints.

IEC 61000

EMC limits, captured as constraints.

IEC 60068

Environmental limits, captured as constraints.

IPC-2228 / IPC-6018

Board-fabrication rules the allocation has to respect.

Embedded RF/radar recipe, extending the electronics recipe

Take an RF sensing module from need to a released baseline with spectrum, EMC, environmental and fabrication constraints carried as first-class, traced obligations.

  1. Frame

    Frame the sensing requirement and the regulatory environment it operates in.

  2. Constrain

    Pull spectrum (ITU), EMC (IEC 61000) and environmental (IEC 60068) limits in as constraints.

  3. Trade

    Trade the RF architecture against those constraints, not around them.

  4. Allocate

    Allocate onto the board with its fabrication rules (IPC-2228 / 6018).

  5. Verify

    Close verification against every regulatory constraint before baseline.

SRR — System Requirements Review

The regulatory constraints have to be in the requirement baseline, not discovered late.

Singular and verifiable

Every requirement is singular and verifiable.

Constraints captured

Spectrum, EMC and environmental limits are captured as constraints.

Verification method

A verification method is assigned to each requirement.

Hazard list

The initial hazard list exists.

The recipe is where a system class encodes its standards; the gate is where a human confirms they made it into the baseline.

In the platform

DjiniousEngineering
The ELANG graph view of the Kestrel-SAR III payload in DjiniousEngineering: components, requirements, tests, actors, a hazard and lifecycle phases connected by implements, satisfies, supplied_by, verifies and mitigates edges, with a conformance-gaps panel at L1 with twelve gaps.
The same model as a graph: each requirement tied to the components that satisfy it and the test that verifies it, with the gaps panel naming the twelve well-formedness gaps still holding it at L1.